Conductive lines or interconnect structures are used to connect devices in integrated circuits and to connect to external pads. Adjacent interconnect lines form parasitic capacitors. The plate area of each plate of the capacitor is the product of the length of the line and its thickness over that length. The capacitances of such capacitors are directly proportional to the area of the capacitor plates and the dielectric constant of the dielectric material disposed between the plates, and are inversely proportional to the distance between the capacitor plates (line-to-line spacing). Thus, as IC's are scaled down in size, the line-to-line spacing decreases. In addition, the number of lines that are needed to interconnect the increased number of devices also increases, resulting in an increase in the line-to-line capacitance. In some high-speed circuits, this interconnect capacitance can be the limiting factor in the speed of the integrated circuit. Thus it is desirable to reduce the interconnect capacitance. Accordingly, low dielectric constant (low k) materials have been increasingly used.
The use of low-k dielectric materials, however, has introduced new problems. Low-k dielectric materials typically have low thermal conductivity, and thus are not good at dissipating heat. On the other hand, with the increase in device density, high currents are conducted by the metal lines in the low-k dielectric layers. Joule heating effect, thus, may occur. The high density of metal lines further worsens the problem. The Joule heating effect causes an increase in the temperature, and in turn significantly affects the reliability of the interconnect structure, and electro-migration and stress-migration effects are worsened. A solution is, thus, needed to solve these problems.